Larger Scheduler buffer (54-entry, up from 26-entry).Increased ROB to 168 entries (From 128).
A 14- to 19-stage instruction pipeline, depending on the micro-operation cache hit or miss.This tighter integration reduces memory latency even more. In contrast, Sandy Bridge's predecessor, Clarkdale, has two separate dies (one for GMCH, one for processor) within the processor package. Integration of the GMCH (integrated graphics and memory controller) and processor into a single die inside the processor package.Up to 8 physical cores, or 16 logical cores through hyper-threading (From 6 core/12 thread).Advanced Vector Extensions (AVX) 256-bit instruction set with wider vectors, new extensible syntax and rich functionality.256-bit/cycle ring bus interconnect between cores, graphics, cache and System Agent Domain.Improved performance for transcendental mathematics, AES encryption ( AES instruction set), and SHA-1 hashing.Sandy Bridge has a single BTB that holds twice as many branch targets as the L1 and L2 BTBs in Nehalem. Sandy Bridge retains the four branch predictors found in Nehalem: the branch target buffer (BTB), indirect branch target array, loop detector and renamed return stack buffer (RSB).Decoded micro-operation cache, and enlarged, optimized branch predictor.Two load/store operations per CPU cycle for each memory channel.Improved 3 integer ALU, 2 vector ALU and 2 AGU per core.Shared 元 cache which includes the processor graphics ( LGA 1155).32 KB data + 32 KB instruction L1 cache and 256 KB L2 cache per core.
Intel demonstrated a Sandy Bridge processor with A1 stepping at 2 GHz during the Intel Developer Forum in September 2009.
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